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8732ay-01 www.idt.com rev. e may 2, 2013 1 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator g eneral d escription the ICS8732-01 is a low voltage, low skew, 3.3v lvpecl clock generator. the ICS8732-01 has two selectable clock inputs. the clk0, nclk0 pair can accept most standard differential input levels. the single ended clock input accepts lvcmos or lvttl input levels. the ICS8732-01 has a fully integrated pll along with frequency configurable outputs. an external feedbackinput and outputs regenerate clocks with ?zero delay?. the ICS8732-01 has multiple divide select pins for each bank of outputs along with 3 independent feedback divide select pins allowing the ICS8732-01 to function both as a frequency multiplier and divider. the pll_sel input can be usedto bypass the pll for test and system debug purposes.in bypass mode, the input clock is routed around the plland into the internal output dividers. features ? ten differential 3.3v lvpecl outputs ? selectable differential clk0, nclk0 or lvcmos/lvttl clk1 inputs ? clk0, nclk0 supports the following input types: lvpecl, lvds, lvhstl, sstl, hcsl ? clk1 accepts the following input levels: lvcmos or lvttl ? maximum output frequency: 350mhz ? vco range: 250mhz to 700mhz ? external feedback for ?zero delay? clock regeneration with configurable frequencies ? cycle-to-cycle jitter: clk0, nclk0, 50ps (maximum) clk1, 80ps (maximum) ? output skew: 150ps (maximum) ? static phase offset: -150ps to 150ps ? lead-free package fully rohs compliant b lock d iagram p in a ssignment 52-lead lqfp 10mm x 10mm x 1.4mm package body y package top view clk_sel clk0 nclk0 clk1 fb_in nfb_in pll_sel div_sela0 div_sela1 div_selb0 div_selb1 fbdiv_sel0 fbdiv_sel1 fbdiv_sel2 mr qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 0 1 pll 0 1 qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 qfb0 nqfb0 qfb1 nqfb1 2 4 6 8 2 4 8 12 4 6 8 10 8 12 16 20 ICS8732-01 14 1 5 1 6 17 1 8 1 9 2 0 21 22 2 3 24 2 5 2 6 1 2 5 6 7 1 0 11 1 2 1 3 38 39 35 34 33 31 30 2 9 2 8 27 v cco q a 0 n q a 1 v ee pll _ se l v ee v cco n q a 2 q a 3 n q a 3 v cco n q b 3 q b 2 v ee v ee mr v cco q b1 n q b 0 q b 0 d iv _ sela1 d iv _ selb0 d iv _ sela0 v cc v ee c lk1 nc lk 0 c lk 0 c lk _ sel v cc a nc d iv _ selb1 v cc f bdiv _ sel2 f bdiv _ sel1 f bdiv _ sel0 n fb _ in f b _ in v cc v ee v cco nq fb0 q fb0 nq fb1 q fb1 v ee 4 8 4 9 50 51 52 47 4 6 4 5 44 4 3 42 41 4 0
8732ay-01 www.idt.com rev. e may 2, 2013 2 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d , 2 3 , 8 , 1 0 4 , 9 3 v o c c r e w o p. s n i p y l p p u s t u p t u o , 3 , 2 5 , 4 , 0 a q n , 0 a q 1 a q n , 1 a q t u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d , 6 , 7 1 , 3 1 , 4 3 , 7 2 2 5 , 5 4 v e e r e w o p. s n i p y l p p u s e v i t a g e n 7l e s _ l l pt u p n ip u l l u p . s r e d i v i d e h t o t t u p n i e h t s a k c o l c e c n e r e f e r d n a l l p e h t n e e w t e b s t c e l e s . l l p s t c e l e s , h g i h n e h w . k c o l c e c n e r e f e r s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 0 1 , 9 2 1 , 1 1 , 2 a q n , 2 a q 3 a q n , 3 a q t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d 4 11 a l e s _ v i dt u p n in w o d l l u p . 3 e l b a t n i d e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5 10 a l e s _ v i dt u p n in w o d l l u p . 3 e l b a t n i d e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 6 2 , 6 1 6 4 v c c r e w o p. s n i p y l p p u s e r o c 8 11 k l ct u p n in w o d l l u p. t u p n i k c o l c e c n e r e f e r l t t v l / s o m c v l 9 10 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 0 20 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 1 2l e s _ k l ct u p n in w o d l l u p . 0 k l c n , 0 k l c s t c e l e s , w o l n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 1 k l c s t c e l e s , h g i h n e h w 2 2v a c c r e w o p. n i p y l p p u s g o l a n a 3 2c nd e s u n u. t c e n n o c o n 4 21 b l e s _ v i dt u p n in w o d l l u p . 3 e l b a t n i d e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5 20 b l e s _ v i dt u p n in w o d l l u p . 3 e l b a t n i d e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 9 2 , 8 2 1 3 , 0 3 , 0 b q n , 0 b q 1 b q n , 1 b q t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d 3 3r mt u p n in w o d l l u p s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a s t u p t u o d e t r e v n i e h t d n a w o l o g o t x q s t u p t u o e u r t e h t g n i s u a c t e s e r e r a e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l n e h w . h g i h o g o t x q n . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e , 6 3 , 5 3 8 3 , 7 3 , 2 b q n , 2 b q 3 b q n , 3 b q t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d , 2 4 , 1 4 4 4 , 3 4 , 1 b f q n , 1 b f q 0 b f q n , 0 b f q t u p t u o . s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o k c a b d e e f l a i t n e r e f f i d 7 4n i _ b ft u p n in w o d l l u p s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f . " y a l e d o r e z " h t i w 8 4n i _ b f nt u p n ip u l l u p s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f . " y a l e d o r e z " h t i w 9 40 l e s _ v i d b ft u p n in w o d l l u p . s r i a p t u p t u o k c a b d e e f l a i t n e r e f f i d r o f e u l a v e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 51 l e s _ v i d b ft u p n in w o d l l u p . s r i a p t u p t u o k c a b d e e f l a i t n e r e f f i d r o f e u l a v e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 52 l e s _ v i d b ft u p n in w o d l l u p . s r i a p t u p t u o k c a b d e e f l a i t n e r e f f i d r o f e u l a v e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
8732ay-01 www.idt.com rev. e may 2, 2013 3 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k t able 3a. c ontrol i nput f unction t able for qa0:qa3 o utputs s t u p n is t u p t u o r ml e s _ l l p1 a l e s _ v i d0 a l e s _ v i d3 a q n : 0 a q n , 3 a q : 0 a q 1x x x w o l 01 0 0 2 / o c v f 01 0 1 4 / o c v f 01 1 0 6 / o c v f 01 1 1 8 / o c v f 00 0 0 2 / k l c _ f e r f 00 0 1 4 / k l c _ f e r f 00 1 0 6 / k l c _ f e r f 00 1 1 8 / k l c _ f e r f t able 3b. c ontrol i nput f unction t able for qb0:qb3 o utputs s t u p n is t u p t u o r ml e s _ l l p1 b l e s _ v i d0 b l e s _ v i d3 b q n : 0 b q n , 3 b q : 0 b q 1x x x w o l 01 0 0 2 / o c v f 01 0 1 4 / o c v f 01 1 0 8 / o c v f 01 1 1 2 1 / o c v f 00 0 0 2 / k l c _ f e r f 00 0 1 4 / k l c _ f e r f 00 1 0 8 / k l c _ f e r f 00 1 1 2 1 / k l c _ f e r f
8732ay-01 www.idt.com rev. e may 2, 2013 4 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator t able 4a. q x o utput f requency w /fb_in = qfb0 or qfb1 s t u p n io c v f n i _ b f2 l e s _ v i d b f1 l e s _ v i d b f0 l e s _ v i d b fe d o m r e d i v i d t u p t u o ) z h m ( 1 k l c ) 1 e t o n ( m u m i n i mm u m i x a m b f q0 0 0 4 5 . 2 6 5 7 1 ) 2 e t o n ( 4 x k l c _ f e r f b f q0 0 1 6 7 6 . 1 47 6 . 6 1 16 x k l c _ f e r f b f q0 1 0 8 5 2 . 1 35 . 7 88 x k l c _ f e r f b f q0 1 1 0 1 5 20 70 1 x k l c _ f e r f b f q1 0 0 8 5 2 . 1 35 . 7 88 x k l c _ f e r f b f q1 0 1 2 1 3 8 . 0 23 3 . 8 52 1 x k l c _ f e r f b f q1 1 0 6 1 2 6 . 5 15 7 . 3 46 1 x k l c _ f e r f b f q1 1 1 0 2 5 . 2 15 30 2 x k l c _ f e r f . z h m 0 0 7 o t z h m 0 5 2 s i e g n a r y c n e u q e r f o c v : 1 e t o n . z h m 5 7 1 s i t p e c c a n a c r o t c e t e d e s a h p e h t t a h t y c n e u q e r f t u p n i m u m i x a m e h t : 2 e t o n t able 3c. c ontrol i nput f unction t able for qfb0, qfb1 s t u p n is t u p t u o r ml e s _ l l p2 l e s _ v i d b f1 l e s _ v i d b f0 l e s _ v i d b f 1 b f q , 0 b f q 1 b f q n , 0 b f q n 1x x x x w o l 01 0 0 0 4 / o c v f 01 0 0 1 6 / o c v f 01 0 1 0 8 / o c v f 01 0 1 1 0 1 / o c v f 01 1 0 0 8 / o c v f 01 1 0 1 2 1 / o c v f 01 1 1 0 6 1 / o c v f 01 1 1 1 0 2 / o c v f 00 0 0 0 4 / k l c _ f e r f 00 0 0 1 6 / k l c _ f e r f 00 0 1 0 8 / k l c _ f e r f 00 0 1 1 0 1 / k l c _ f e r f 00 1 0 0 8 / k l c _ f e r f 00 1 0 1 2 1 / k l c _ f e r f 00 1 1 0 6 1 / k l c _ f e r f 00 1 1 1 0 2 / k l c _ f e r f
8732ay-01 www.idt.com rev. e may 2, 2013 5 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator t able 5a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i c c t n e r r u c y l p p u s r e w o p 5 6 1a m i a c c t n e r r u c y l p p u s g o l a n a 5 1a m t able 5b. lvcmos/lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 1 k l c2v c c 3 . 0 +v , l e s _ l l p , l e s _ k l c , x b l e s _ v i d , x a l e s _ v i d r m , x l e s _ v i d b f 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 1 k l c3 . 0 -3 . 1v , l e s _ l l p , l e s _ k l c , x b l e s _ v i d , x a l e s _ v i d r m , x l e s _ v i d b f 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i 1 k l c , r m , l e s _ k l c , x b l e s _ v i d , x a l e s _ v i d x l e s _ v i d b f v c c v = n i v 5 6 4 . 3 =0 5 1a l e s _ l l pv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i 1 k l c , r m , l e s _ k l c , x b l e s _ v i d , x a l e s _ v i d x l e s _ v i d b f v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a l e s _ l l p v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 42.3c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8732ay-01 www.idt.com rev. e may 2, 2013 6 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator t able 5d. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c t able 7. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 5 3z h m t ) ? (1 e t o n ; t e s f f o e s a h p c i t a t s , v 3 . 3 = l e s _ l l p z h m 0 0 4 = o c v f , z h m 0 0 1 = f e r f 0 5 1 -0 5 1s p t ) o ( k s4 , 3 , 2 e t o n ; w e k s t u p t u o 0 5 1s p t ) c c ( t i j ; r e t t i j e l c y c - o t - e l c y c 3 e t o n , 0 k l c k l c n 0 5s p 1 k l c 0 8s p t l e m i t k c o l l l p 0 1s m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p c d oe l c y c y t u d t u p t u ot u o f z h m 5 7 18 42 5% t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u l a n g i s t u p n i k c a b d e e f d e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 1 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m : 3 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t . n o i t a r u g i f n o c 4 y b e d i v i d n i s t u p t u o l l a : 4 e t o n t able 6. pll i nput r eference c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f f e r y c n e u q e r f e c n e r e f e r t u p n i 0 0 2z h m t able 5c. d ifferential dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i n i _ b f , 0 k l cv c c v = n i v 5 6 4 . 3 =0 5 1a n i _ b f n , 0 k l c nv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i n i _ b f , 0 k l cv c c v , v 5 6 4 . 3 = n i v 0 =5 -a n i _ b f n , 0 k l c nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v v s i n i _ b f n , n i _ b f r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n c c . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 -
8732ay-01 www.idt.com rev. e may 2, 2013 7 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator p arameter m easurement i nformation c ycle - to -c ycle j itter s tatic p hase o ffset o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g t sk(o) nqx qx nqy qy d ifferential i nput l evel o utput s kew 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl v cmr cross points v pp v ee clk0, fb_in nclk0, nfb_in v cc ? ? ? ? nqa0:nqa3, nqb0:nqb3, nqfb0, nqfb1 qa0:qa3, qb0:qb3, qfb0, qfb1 nclk0 clk0, clk1 nfb_in fb_in ? ? t (?) v oh v ol v oh v ol -1.3v 0.165v 2v o utput d uty c ycle /p ulse w idth /p eriod t pw t period t pw t period odc = x 100% nqa:nqa3, nqfb0, nqfb1 qa:qa3, qfb0, qfb1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 v ee v cc , v cca , v cco
8732ay-01 www.idt.com rev. e may 2, 2013 8 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator a pplication i nformation v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 2b. lvpecl o utput t ermination f igure 2a. lvpecl o utput t ermination drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 2a and 2b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc
8732ay-01 www.idt.com rev. e may 2, 2013 9 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator f igure 4c. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 4b. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 4d. clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver f igure 4a. clk/ n clk i nput d riven by lvhstl d river 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS8732-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc, v cca and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 3 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. f igure 3. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc p ower s upply f iltering t echniques component to confirm the driver termination requirements. for example in figure 4a, the input termination applies for lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation.
8732ay-01 www.idt.com rev. e may 2, 2013 10 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator c16 10uf u1 ICS8732-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 vcco qa0 nqa0 qa1 nqa1 vee pll_sel vcco qa2 nqa2 qa3 nqa3 vee div_sela1 div_sela0 vcc vee clk1 nclk0 clk0 clk_sel vcca nc div_selb1 div_selb0 vcc vcco nqb3 qb3 nqb2 qb2 vee mr vcco nqb1 qb1 nqb0 qb0 vee vee fbdiv_sel2 fbdiv_sel1 fbdiv_sel0 nfb_in fb_in vcc vee nqfb0 qfb0 nqfb1 qfb1 vcco to logic input pins r13 1k c7 0.1uf rd2 1k r7 50 logic input pin examples r14 1k + - r7 10 div_sela1 vcc vcc fbdiv_sel2 c4 0.1uf vcc=3.3v r9 50 vcc r12 50 + - r1 50 c5 0.1uf vcca r6 50 (u1-1) sp = spare (i.e. not intstalled) (u1-39) zo = 50 div_selb1 r2 50 zo = 50 vcc set logic input to '0' zo = 50 c3 0.1uf bypass capacitors located near the power pins zo = 50 zo = 50 zo = 50 to logic input pins div_sela0 fbdiv_sel1 r11 50 ru2 sp (u1-16) c2 0.1uf r8 50 div_selb0 c8 0.1uf set logic input to '1' fbdiv_sel0 c6 0.1uf rd1 sp (u1-32) c11 0.1uf ru1 1k (u1-26) vcc (u1-40) vcc r10 50 r3 50 (u1-46) lvpecl (u1-8) c1 0.1uf vcc r5 50 r4 50 l ayout g uideline figure 5 shows a schematic example of the ICS8732-01. in this example, the clk0/nclk0 input is selected. the decoupling ca- pacitors should be physically located near the power pin. for ICS8732-01, the unused outputs can be left floating. f igure 5. ICS8732-01 lvpecl b uffer s chematic e xample
8732ay-01 www.idt.com rev. e may 2, 2013 11 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS8732-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS8732-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 165ma = 572mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 10 * 30mw = 300mw total power _max (3.465v, with all outputs switching) = 572mw + 300mw = 872mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for the devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4c/w per table 8 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.872w * 36.4c/w = 101.7c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) t able 8. t hermal r esistance ja for 52- pin lqfp, f orced c onvection 0 200 500 single-layer pcb, jedec standard test boards 58. 0c/w 47.1c/w 42.0c/w multi-layer pcb, jedec standard test boards 42. 3c/w 36.4c/w 34.0c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8732ay-01 www.idt.com rev. e may 2, 2013 12 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
8732ay-01 www.idt.com rev. e may 2, 2013 13 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator r eliability i nformation t ransistor c ount the transistor count for ICS8732-01 is: 4916 t able 9. ja vs . a ir f low t able for 52 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 58. 0c/w 47.1c/w 42.0c/w multi-layer pcb, jedec standard test boards 42. 3c/w 36.4c/w 34.0c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8732ay-01 www.idt.com rev. e may 2, 2013 14 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator p ackage o utline - y s uffix for 52 l ead lqfp t able 10. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c c b m u m i n i ml a n i m o nm u m i x a m n 2 5 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 2 2 . 02 3 . 08 3 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 2 1 1 d c i s a b 0 0 . 0 1 e c i s a b 0 0 . 2 1 1 e c i s a b 0 0 . 0 1 e c i s a b 5 6 . 0 l 5 4 . 0- -5 7 . 0 0 - - 7 c c c - -- -8 0 . 0
8732ay-01 www.idt.com rev. e may 2, 2013 15 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator t able 11. o rdering i nformation while the information presented herein has been checked for both accur acy and reliability, integrated device technology, inc. ( idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are impl ied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other extraordinary environmental requirement s are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use i n life support devices or critical medical instruments. part/order number marking package shipping packaging temperature 8732ay-01lf ics8732ay-01lf 52 lead "lead free" lqfp tube 0c to +70c 8732ay-01lft ics8732ay-01lf 52 lead "lead free" lqfp 500 tape and reel 0c to +70c note: "lf" suffix to the part number are the pb-free configuration, rohs compliant
8732ay-01 www.idt.com rev. e may 2, 2013 16 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b 2 t a 4 t 1 3 4 5 8 . z h m 0 5 2 o t z h m 0 0 2 m o r f . n i m o c v d e g n a h c - n o i t c e s s e r u t a e f c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i . f p 4 l a c i p y t o t f p 4 . x a m m o r f h t i w e t a l e r r o c o t n m u l o c . n i m 1 k l c e h t d e g n a h c - e l b a t y c n e u q e r f t u p t u o x q . e g n a h c o c v e h t v d e g n a h c - s g n i t a r m u m i x a m e t u l o s b a o i o t o s u o u n i t n o c d e d u l c n i d n a t n e r r u c e g r u s d n a t n e r r u c d e d d a e c a f r e t n i t u p n i k c o l c l a i t n e r e f f i d . n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t n i 3 0 / 0 2 / 5 ca 5 t5 o t . x a m a m 0 4 2 m o r f e e i d e g n a h c - e l b a t s c i t s i r e t c a r a h c c d y l p p u s r e w o p . x a m a m 5 1 o t . x a m a m 4 1 m o r f a c c i d n a , . x a m a m 5 6 1 n o i t c n u j d n a n o i t a p i s s i d r e w o p d e t a l u c l a c e r - s n o i t a r e d i s n o c r e w o p . a 5 e l b a t h t i w d n o p s e r r o c o t s e r u t a r e p m e t 3 0 / 3 2 / 6 c 8 0 1 . s m a r g a i d n o i t a n i m r e t t u p t u o l c e p v l d e t a d p u . t u o y a l c i t a m e h c s d e d d a 3 0 / 4 2 / 9 c1 . l e s _ k l c o t l e s _ f e r d e g n a h c - m a r g a i d k c o l b 4 0 / 3 / 3 c 1 1 t5 1 m o r f 0 0 5 d a e r o t t n u o c l e e r & e p a t d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o . 0 0 0 1 4 0 / 9 2 / 4 ca 4 t4 . " z h m 5 7 1 " o t " z h m 0 0 2 " m o r f 2 e t o n d e g n a h c - e l b a t y c n e u q e r f t u p t u o x q 4 0 / 9 1 / 0 1 c 1 1 t 1 5 1 . t e l l u b e e r f d a e l d e d d a - n o i t c e s s e r u t a e f . e t o n d n a r e b m u n t r a p e e r f d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 3 2 / 5 ca 5 t5 i d e t c e r r o c - e l b a t s c i t s i r e t c a r a h c c d y l p p u s r e w o p e e i d a e r o t c c .5 0 / 1 3 / 5 d d 5 t6 2 1 - 1 1 - e l b a t s c i t s i r e t c a r a h c c d l c e p v lv d e t c e r r o c h o v m o r f . x a m o c c o t v 0 . 1 - v o c c . v 9 . 0 - v t c e l f e r o t n o i t a p i s s i d r e w o p d e t c e r r o c - s n o i t a r e d i s n o c r e w o p h o e l b a t n i x a m . d 5 7 0 / 3 1 / 4 e1 1 t5 1 7 1 . s c i m o r f t d i h t i w r e t o o f / r e d a e h s ' t e e h s a t a d d e t a d p u . n m u l o c r e b m u n r e d r o / t r a p m o r f x i f e r p s c i d e v o m e r . e g a p t c a t n o c d e d d a 0 1 / 1 3 / 7 e d 5 t9 v = m u m i x a m h o v o c c 9 . 0 - 3 1 / 2 / 5
8732ay-01 www.idt.com rev. e may 2, 2013 17 ICS8732-01 l ow v oltage , l ow s kew 3.3v lvpecl c lock g enerator we?ve got your timing solution. sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 tech support netcom@idt.com 6024 silver creek valley road san jose, ca 95138 ? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or m ay be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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